Generally, the implementation of a phase-locked loop (PLL) requires the acquisition of an appropriate frequency and phase using an internal ring oscillator. Analog phase-locked loops typically use a voltage-controlled oscillator (VCO) to generate a period signal that is "locked" to a reference clock signal. The frequency of the VCO is modulated by an analog voltage adjusted via a feedback mechanism. Typically, the feedback mechanism is supplied from a sequential phase/frequency detector. The sequential phase/frequency detector outputs an "up" or "down" pulse proportional to phase-error width and in the direction required to pull in the frequency of the VCO output signal to the target reference clock signal. The output of a sequential phase/frequency detector usually enables a charge pump driving to a loop filter (RC), which in turn controls the frequency of the VCO. The detector outputs can be arbitrarily small, and thus there is usually a dead band associated with such a detector where, for a certain window of time, there is no detectable output. Accordingly, during the dead band ("window width"), the PLL can detect neither "up" nor "down" pulses for a phase/frequency error of a magnitude equal to or less than the window width. This technique has been used in many applications, and requires careful tuning to maintain the right damping characteristics.
The gain of the VCO is defined as dF/dV (the change in VCO frequency per change in the analog control voltage). The maximum change in frequency occurs when there is a maximum amount of phase error during a given cycle (maximum dV). The change in analog control voltage (dV), depends on many parameters, such as the charge pump, loop filter, etc. Consequently, the loop gain of the PLL requires careful tuning of these parameters to maintain the right damping characteristics. If the gain is too high, the PLL will be unstable, resulting in excessive jitter or loss of lock. Conversely, if the gain is too low, the PLL may not be able to track frequency drift due to fluctuations in the reference frequency, V.sub.DD, or temperature. Thus, the gain (dF/dV) must be constrained, which causes the PLL to suffer unnecessary time penalties during phase and frequency acquisition.
In today's high performance microprocessors, an emphasis is placed on low-power operation without compromising the high performance of the microprocessor. As portable applications proliferate, it is desirable to incorporate power management techniques to reduce power and extend battery life. One of these techniques entails shutting down the microprocessor while statically maintaining code. This state is called low power stop (LPSTOP), where the microprocessor is completely quiescent, using no power. In portable applications, it is desirable to be able to force microprocessors in and out of the low-power states (LPSTOP) very rapidly. Historically, the largest performance penalty in cycling in and out of LPSTOP has been the amount of time the PLL requires to re-acquire phase lock. Essentially, the frequency at which LPSTOP can be used is dictated by how fast a PLL can acquire (re-acquire) phase-lock. Thus, slow lock times reduce the frequency of entering/leaving LPSTOP and result in increased power dissipation. Fast lock times increase the frequency of entering LPSTOP, and reduce power dissipation. Known analog PLL's have long lock times due to the constraints imposed upon the gain. It is desirable, therefore, to have a PLL capable of very fast frequency acquisition which reduces the phase acquisition time penalty, and thereby provides rapid exit from a low-power state.